The present invention relates to, for example, a disc reproducing device of an optical CD (compact disc) system, and particularly, to a disc reproducing device so designed that the reproducing signal is not interrupted even if an erroneous track jump occurs during reproduction.
As is well known in the field of audio apparatus, digital record reproducing systems have been generally adopted for the purpose of reproducing recorded data of high density and high fidelity. In these systems, audio signals are converted into digitized data by a PCM (Pulse Code Modulation) technique and this data is recorded on a recording medium, such as a disc or a magnetic tape, to be reproduced. Among these systems, the compact disc is mainly used at present. In this case, a binary digit (bit) string corresponding to digitized data is formed on a disc of about 12 cm in diameter, and is optically read.
A disc reproducing device for reproducing the compact disc as described above, moves an optical pickup provided with a semiconductor laser and a photoelectric conversion device in a constant linear velocity tracking system (CLV) from the inner periphery side to the outer periphery side of the disc, and by rotating the compact disc the data recorded on the compact disc may be read.
On the compact disc, digital audio data (main information data) in the form of analog audio signals which have been PCM modulated in 8 bits is recorded. In this case, the digital audio data is recorded in the form of units of 24 symbols, each symbol constituting 8 bits. Each unit is called a frame or word and this frame is repeated.
In particular, as shown in FIG. 1, digital audio data (hereinafter called a word) Wm is supplied to a C2 system parity generating circuit 101 through a scramble circuit 102, and parity data Qm of 4 symbols (one symbol is 8 bits) for correcting the C2 system error is generated. The word Wm of 24 symbols and the parity data Qm of 4 symbols are supplied to a C1 system parity generating circuit 103 through an interleave circuit 104, and parity data Pm of 4 symbols (one symbol is 8 bits) for correcting C1 system error is generated.
After that, subcode data of 8 bits is added to the word Wm of 24 symbols and data of 32 symbols which is constituted by the parity data Pm and Qm of 4 symbols, through a first one frame delay circuit 105. The subcode data and the data of 32 symbols are EFM (Eight to Fourteen Modulation) modulated. Margin bits of 3 bits are interposed between each symbol of 14 bits, and this combined data is modulated. A frame synchronizing signal of 24 bits is added to the combined modulated data. The data of 588 bits obtained in such a manner as described above is recorded on the disc as one frame.
In this case, the bit clock is 4.32 MHz, and the data is recorded on the disc at 136 .mu.sec (7.35 kHz) per one frame. Also, for subcode data, one subcode frame is constituted of 98 frames and the data is recorded on the disc at 75 Hz (13.3 msec) per one subcode frame.
During reproduction, the disc reproducing device EFM demodulates the digitized data read from the compact disc and then separates it into the word component, including the parity data Pm and Qm, and the subcode data component. Among these components, the word component is supplied to a C1 system error correction circuit 106 through a second one frame delay circuit 107, as shown in FIG. 2, and error correction processing is performed on the basis of the parity data Pm.
After that, the word Wm of 24 symbols and the parity Qm of 4 symbols are supplied to a C2 system error correction circuit 108 through a deinterleave circuit 109, and the error correction processing is performed on the basis of the parity data Pm. The word Wm of 24 symbols is supplied to an A/D (digital/analog) conversion circuit system and analog signal processing circuit system (not shown) through a descramble circuit 110, and reproduced into an analog signal.
The subcode data component is constituted of 8 bit data called P, Q, R, S, T, U, V, and W per one frame, and, as described above, one subcode frame is constituted by 98 bits. For the subcode data, two bits (bit No. "0" and "1") at the top of one subcode frame are subcode frame synchronous patterns S0 and S1 and the remaining 96 bits are substantial data components.
The subcode data P is provided for identification of each successive recorded segment. For example, "1" shows the start and "0" continued play. The subcode data Q is called address data. In the program area (radius 25 mm to 58 mm) of a disc, they show a so-called music number or track number (TNO), a so-called phrase number (index), and a lapse of time. In the lead-in area (radius 23 mm to 25 mm) of a disc, they show so-called table of contents data (TOC data) for showing a start address for each segment of recorded data, such as music.
Other subcode data R to W of 6 bits are provided for recording color graphic image data at a current standard.
In the processing as described in FIG. 2, which is performed in the disc reproducing device, a read/write memory (hereinafter called RAM) is used. That is, the EFM modulated word components are successively written in the RAM. After the C2 system error correction processing, they are read from the RAM and output to the A/D conversion circuit system.
In this case, the address to be supplied to the RAM is classified into one of the following four kinds. These addresses are the Wr address for writing the EFM modulated data in the RAM, the C1 address for reading the C1 system data to detect an error of the C1 system from the data written in the RAM and for writing in and reading from the RAM to correct the detected erroneous data, the C2 address for reading the C2 system data to detect an error of the C2 system data from the data written in the RAM and for writing in and reading from the RAM to correct the detected erroneous data, and the Re address for reading the data from the RAM to output to the A/D conversion circuit system.
FIG. 3 is a diagram showing the conventional address generating means for generating each address of the Wr, C1, C2, and Re. In this case, to make the description easily understandable, the data in one frame is assumed to be 6 symbols of U0 to U5 and interleave processing also is assumed as a delay of one frame.
Each address described above is constituted of 4 bit frame addresses A0 to A3 and 3 bit symbol addresses A4 to A6. The symbol addresses A4 to A6 are generated by a symbol address generating circuit 115 consisting of counters 111 and 112, a correction symbol address register 113, and a selector 114.
In this case, the counter 111 indicates the symbol address of each symbol U0 to U5 at the generation of the Wr address, and has the values of 0 to 5. The correction symbol address register 113 indicates the symbol address of the symbols U0 to U5 where an error is detected by error detection of the C1 or C2 system.
The contents of one of the counters 111 and 112 and the correction symbol address register 113 is selected by the selector 114 according to the timing of each data processing and output.
The frame addresses A0 to A3 are generated from a circuit consisting of counters 116 and 117, a read-only memory (hereinafter referred as ROM) 118, arithmetic circuits 119 and 120, and a selector 121. In this case, the counter 116 is a hexadecimal counter indicating the frame address of each symbol U0 to U5 at the generation of the Wr address and resets each time 6 symbols U0 to U5 per frame are finished. The counter 117 is a hexadecimal counter indicating the frame address of each symbol U0 to U5 at the generation of the C1, C2, and Re and resets when error correction of one frame is finished. The ROM 118 inputs the symbol addresses A4 to A6 and outputs the fixed value N to be described later.
The arithmetic circuit 119 subtracts the contents B of the counter 117 from the contents A of the counter 116 and the arithmetic circuit 120 subtracts the fixed value N of the ROM 118 from the contents B of the counter 117.
In this case, the calculation is performed by a modulo of hexadecimal (16). For example, in the calculation of B-2, if B=1, the following value is obtained, EQU B-2=15.
The contents A of the counter 116 become the frame address of Wr, the contents B of the counter 117 become the frame address of C1, the result of subtraction of the arithmetic circuit 120 becomes each frame address of C2 and Re and these addresses are selected by the selector 121 and output. In this case, each frame address of Wr, C1, C2, and Re is generated with relation to each symbol U0 to U5, as shown in FIG. 4.
The counter 116 counts the clock generated on the basis of the frame synchronizing signal of the EFM data reproduced from the disc, and generates the frame address of Wr. As a result, jitter occurs during the write-in processing into the RAM of the modulated word components on the basis of the contents A (frame address of Wr) of the counter 116.
The counters 117, 111, and 112 count the reference clock which is generated by a crystal on a fixed cycle. The counters 117, 111, and 112 also generate the frame addresses of C1, C2, and Re. Therefore, the frame address of Wr, which is generated by the counter 116, has a jitter component when compared with the frame address of C1, which is generated by the counter 117.
FIG. 5 shows a memory map of data in the RAM. In this map, the positions of the data specified by each address of Wr, C1, C2, and Re are shown as Wr, C1, C2, and Re, respectively. In this case, absorption of jitter for +4 frames and -3 frames is performed on the basis of the frame address [11] of Wr.
For this reason, in the initial state A-4 is preset in the counter 117 by the arithmetic circuit 119. Also, always A-B is calculated and the speed of rotation of the disc is controlled by the arithmetic circuit 119 so that, EQU A-B=4
when the value of A-B becomes less than 0 or more than 9. Buffer-over is generated and the arithmetic circuit 119 outputs buffer-over signal OV1 to the counter 117. Accordingly, in the counter 117, A-4 is preset in the same manner, as in the initial state.
FIG. 5 shows the processing state obtained when the contents A of the counter 116 is [11] and the contents B of the counter 117 is [7]. EFM modulated data is written in the position shown with frame address [11] (indicated as Wr in the drawing). Also, write and read operations for error correction processing of the C1 system are performed at the position shown with frame address [7] (indicated as C1 in the drawing).
Further, write and read for error correction processing of C2 is performed at the position shown with frame address [B-6], [B-5], [B-4], [B-3], [B-2], and [B-1], that is [1], [2], [3], [4], [5], and [6] (indicated as C2 in the drawing) to the symbols U0 to U5. Also, reading of the data when error correction processing is finished is performed at the position shown with frame address [B-7], [B-6], [B-5], [B-4], [B'3], and [B-2], that is, [0], [1], [2], [3], [4], and [5] (indicated as Re in the drawing) to the symbols U0 to U5.
In this case, as in the disc reproducing device, when an optical pickup traces tracks formed on a compact disc and reads data, an objective lens, which is provided in the optical pickup as a pickup device, sometimes jumps in error from the track it is tracing at present to another track by a shock from outside, that is, a track jump occurs. When such a track jump occurs, conventionally the objective lens is controlled to automatically return to the original position by using the address data obtained in the subcode data so that reproducing operation is continued.
To describe more definitely, as shown in FIG. 6(a), it is assumed that an objective lens tracing the track N jumps to the track M at time ta by external vibration. As a result, the data of the track M is read through the objective lens, the distance to the original track N is calculated on the basis of the address data of the subcode data and the objective lens is moved to the original track N at time tb.
In this case, the data served for the C1 system error correction processing is varied, as shown in FIG. 6(b). In FIG. 6(b), the data is sent out in the order of U0, . . . , U5, 2.multidot.U0, . . . , 2.multidot.U5, 3.multidot.U0, . . . , 3.multidot.U5, . . . . In this case, if the objective lens jumps at the break point from the track N to the track M, errors are not detected in the C1 system.
When deinterleave processing is provided to the data, the data arrangement becomes as shown in FIG. 6(c) and when error correction of the C2 system is performed in this state, the error of the C2 system is detected in the frame (indicated with mark [X] in the drawing) where the data of the track N and the data of the track M are mixed. However, in the frame (indicated with mark [o] in the drawing) where the data of the track N and the data of the track M are not mixed, errors are not detected including the data of different tracks.
As described above, for the error correction of the C2 system in the frame where the data of the track N and the data of the track M are mixed, the possibility of error correction is high, and the muting processing of the data of this portion has generally been performed without performing error correction processing.
As a result, the audio signal becomes such as shown in FIG. 7(a). The audio signal obtained by reproducing the track M is causes an erroneous sound if it output. Therefore, practically, data obtained by reproducing the track M is muted, and, as shown in FIG. 7(b), the data read in the duration until the pickup returns to the original position after the track jump is muted.
When performing the operation of returning the pickup to the original position after the track jump, the detection as to whether track jump has occurred and whether the pickup has returned to the original position is performed by reading the address data of subcode data. For reading the address data of subcode data, it is necessary to read the subcode frame synchronizing signal generated from the subcode frame synchronizing patterns S0 and S1.
As shown in FIG. 8(a), therefore, if the subcode frame synchronizing signal can immediately be read at the time point when the pickup jumps in the track M, the pickup can return to the original track N in a short time, also as shown in FIG. 8(b), the muting period of audio signal can be shortened. However, it is very rare that track jump occurs at such an ideal timing. For example, as shown in FIG. 9(a), just after subcode frame synchronizing signal is generated at the time point when the pickup jumps in the track M or when an error is generated in the subcode data read after the pickup returns to the original track N, the muting period of the audio signal is much longer, as shown in FIG. 7(b).
Thus, an interruption in the sound arises, causing listeners to become uncomfortable.
As described above, in a conventional disc reproducing device, there is a problem in that data is muted during the period until a pickup returns to the original track when a track jump occurs, and a sound interval arises when the time required until the pickup returns to the original track is too long.
The present invention has been made in considering the matters described above and its object is to provide a very satisfactory disc reproducing device where no interruption occurs in the reproduction of data during the duration until the pickup returns to the original track after a the track jump.